PDM31532 PDM31532 64K x 16 CMOS 3.3V Static RAM 1 Features Description n High-speed access times The PDM31532 is a high-performance CMOS static 2 RAM organized as 65,536 x 16 bits. The PDM31532 - Coml: 9, 10, 12, 15 and 20 ns features low power dissipation using chip enable - Ind: 12, 15 and 20 ns (CE) and has an output enable input (OE) for fast n Low power operation (typical) memory access. Byte access is supported by upper - PDM31532LA and lower byte controls. 3 Active: 200 mW Standby: 10 mW The PDM31532 operates from a single 3.3V power - PDM31532SA supply and all inputs and outputs are fully TTL- compatible. Active: 250 mW 4 Standby: 20 mW The PDM31532 is available in a 44-pin 400 mil plas- n High-density 64K x 16 architecture tic SOJ and a plastic TSOP (II) package for high- n 3.3V ( 0.3V) power supply density surface assembly and is suitable for use in n Fully static operation high-speed applications requiring high-speed 5 storage. n TTL-compatible inputs and outputs n Output buffer controls: OE n Data byte controls: LB, UB n Packages: 6 Plastic SOJ (400 mil) - SO Plastic TSOP - T (II) 7 Functional Block Diagram Vcc 8 Vss Memory A8-A0 Cell Array 256 x 128 x 32 32K x 32 9 Data Input/ I/O15-I/O0 Sense Amp Output 10 Buffer Column Decoder WE 11 OE Control UB Column Logic Address LB Clock Buffer CE Generator 12 A15-A9 Rev. 4.3 - 3/27/98 1 Row Address Buffer Row Decoder PDM31532 Pin Conguration TSOP (II) SOJ A4 44 A5 1 A4 1 44 A5 A3 43 A6 2 A3 43 2 A6 A2 42 3 A7 A2 42 A7 3 A1 41 OE 4 A1 41 OE 4 40 A0 UB 40 5 A0 5 UB 39 CE LB 6 39 CE 6 LB 38 I/O0 I/O15 7 38 I/O0 7 I/O15 37 I/O1 8 I/O14 37 I/O1 8 I/O14 I/O2 36 I/O13 9 I/O2 36 I/O13 9 I/O3 35 I/O12 10 I/O3 35 I/O12 10 Vcc 34 Vss 11 Vcc 34 Vss 11 Vss 33 Vcc 12 Vss 33 Vcc 12 I/O4 32 13 I/O11 I/O4 32 13 I/O11 I/O5 14 31 I/O10 I/O5 14 31 I/O10 I/O6 30 I/O9 15 I/O6 15 30 I/O9 I/O7 29 I/O8 16 I/O7 29 I/O8 16 WE NC 17 28 WE NC 17 28 A15 18 A8 27 A15 18 A8 27 A14 A9 19 26 A14 A9 19 26 A13 A10 20 25 A13 25 A10 20 A12 24 A11 21 A12 21 24 A11 NC 22 NC 23 NC 22 NC 23 Pin Description Name Description A15-A0 Address Inputs I/O15-I/O0 Data Inputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input LB, UB Data Byte Control Inputs NC No Connect V Ground ss V Power (+3.3V) CC (1) Capacitance (T = +25 C, f = 1.0 MHz) A Symbol Parameter Conditions Max. Unit C Input Capacitance V = V 6pF IN IN SS C Output Capacitance V = V 8pF I/O I/O SS NOTE: 1. This parameter is determined by device characterization, but is not production tested. 2 Rev. 4.3 - 3/27/98