74LVCV2G66DC,125 Nexperia

74LVCV2G66 Overvoltage tolerant bilateral switch Rev. 9 1 April 2021 Product data sheet 1. General description The 74LVCV2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVCV2G66 provides two single pole single throw analog or digital switches. Each switch includes an overvoltage tolerant input/output terminal (pin nZ), an output/input terminal (pin nY) and low-power active HIGH enable input (pin nE). The overvoltage tolerant switch terminals allow the switching of signals in excess of V . The CC low-power enable input eliminates the necessity of using current limiting resistors in portable applications when using control logic signals much lower than V . These inputs are also CC overvoltage tolerant. 2. Features and benefits Wide supply voltage range from 2.3 V to 5.5 V Ultra low-power operation Very low ON resistance: 8.0 (typical) at V = 2.7 V CC 7.5 (typical) at V = 3.3 V CC 7.3 (typical) at V = 5.0 V. CC 5 V tolerant input for interfacing with 5 V logic High noise immunity Switch handling capability of 32 mA CMOS low-power consumption Latch-up performance exceeds 250 mA Incorporates overvoltage tolerant analog switch technology Switch accepts voltages up to 5.5 V independent of V CC Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVCV2G66DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74LVCV2G66GT -40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mmNexperia 74LVCV2G66 Overvoltage tolerant bilateral switch 4. Marking Table 2. Marking codes Type number Marking code 1 74LVCV2G66DC Y66 74LVCV2G66GT Y66 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1Y 1Z 1 1 1E X1 2Z 2Y 1 1 2E X1 001aag497 001aah808 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Z Y E V CC 001aaa532 Fig. 3. Logic diagram (one switch) 6. Pinning information 6.1. Pinning 74LVCV2G666 1Z 1 8 V CC 1Y 2 7 1E 74LVCV2G66 2E 3 6 2Y 1Z 1 8 V CC 1Y 2 7 1E GND 4 5 2Z 2E 3 6 2Y GND 4 5 2Z aaa-018593 Transparent top view 001aai213 Fig. 4. Pin configuration SOT765-1 (VSSOP8) Fig. 5. Pin configuration SOT833-1 (XSON8) 74LVCV2G66 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 9 1 April 2021 2 / 19