GTL2010 10-bit bidirectional low voltage translator Rev. 06 3 March 2008 Product data sheet 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2010 provides 10 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin. When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V by CC the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control. All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benet over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator s transistors provide excellent ESD protection to lower voltage devices and at the same time protect less ESD-resistant devices. 2. Features n 10-bit bidirectional low voltage translator n Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels n Provides bidirectional voltage translation with no direction pin n Low 6.5 ON-state resistance (R ) between input and output pins (Sn/Dn) on n Supports hot insertion n No power supply required: will not latch up n 5 V tolerant inputs n Low standby current n Flow-through pinout for ease of printed-circuit board trace routing n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Packages offered: TSSOP24, HVQFN24GTL2010 NXP Semiconductors 10-bit bidirectional low voltage translator 3. Applications n Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 1.0 V to 5.0 V to any voltage from 1.0 V to 5.0 V n The open-drain construction with no direction pin is ideal for bidirectional low voltage 2 (for example, 1.0 V, 1.2 V, 1.5 V or 1.8 V) processor I C-bus port translation to the 2 normal 3.3 V and/or 5.0 V I C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels 4. Ordering information Table 1. Ordering information Type number Package Name Description Version GTL2010PW TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm GTL2010BS HVQFN24 plastic thermal enhanced very thin quad at package SOT616-1 no leads 24 terminals body 4 4 0.85 mm 4.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range GTL2010PW GTL2010 - 40 C to +85 C GTL2010BS 2010 - 40 C to +85 C 5. Functional diagram DREF GREF D1 D10 SREF S1 S10 002aac059 Fig 1. Functional diagram GTL2010 6 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 3 March 2008 2 of 20