PE43713 Product Specification UltraCMOS RF Digital Step Attenuator, 9 kHz6 GHz Features Figure 1 PE43713 Functional Diagram Flexible attenuation steps of 0.25 dB, 0.5 dB and 1 dB up to 31.75 dB Switched Attenuator Array RF RF Glitch-less attenuation state transitions Input Output Monotonicity: 0.25 dB up to 4 GHz, 0.5 dB up to 5 GHz and 1 dB up to 6 GHz Extended +105 C operating temperature Parallel and Serial programming interfaces with Serial Addressability Packaging32-lead 5 5 mm QFN Parallel Control Applications 7 Test and measurement (T&M) Serial In Control Logic Interface General purpose RF attenuator CLK LE (optional) A0 A1 A2 P/S V SS EXT Product Description The PE43713 is a 50 , HaRP technology-enhanced, 7-bit RF digital step attenuator (DSA) that supports a broad frequency range from 9 kHz to 6 GHz. It features glitch-less attenuation state transitions, supports 1.8V control voltage and includes an extended operating temperature range to +105 C and optional V bypass SS EXT mode to improve spurious performance, making this device ideal for test and measurement (T&M). The PE43713 is a pin-compatible upgraded version of the PE43703. An integrated digital control interface supports both Serial Addressable and Parallel programming of the attenuation, including the capability to program an initial attenuation state at power-up. The PE43713 covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB and 1dB steps. It is capable of maintaining 0.25 dB monotonicity through 4 GHz, 0.50 dB monotonicity through 5 GHz and 1 dB monotonicity through 6 GHz. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE43713 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. 2017, Peregrine Semiconductor Corporation. All rights reserved. Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-84877-2 (1/2018) www.psemi.comPE43713 UltraCMOS RF Digital Step Attenuator Peregrines HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Optional External V Control SS For proper operation, the V control pin must be grounded or tied to the V voltage specified in Table 2. SS EXT SS When the V control pin is grounded, FETs in the switch are biased with an internal negative voltage SS EXT generator. For applications that require the lowest possible spur performance, V can be applied externally SS EXT to bypass the internal negative voltage generator. Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 Absolute Maximum Ratings for PE43713 Parameter/Condition Min Max Unit Supply voltage, V 0.3 5.5 V DD Digital input voltage 0.3 3.6 V RF input power, 50 9 kHz48 MHz Figure 5 dBm +31 dBm >48 MHz6 GHz Storage temperature range 65 +150 C (1) 3000 V ESD voltage HBM, all pins (2) 1000 V ESD voltage CDM, all pins Notes: 1) Human body model (MILSTD 883 Method 3015). 2) Charged device model (JEDEC JESD22C101). Page 2 DOC-84877-2 (1/2018) www.psemi.com