859S0212BGILF Renesas

VCC TAP ICS859S0212I 2:2, Differential-to-LVPECL/LVDS Clock Multiplexer DATA SHEET General Description Features The ICS859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock High speed 2:1 differential multiplexer with a 1:2 fanout buffer Multiplexer which can operate up to 3GHz. The ICS859S0212I has 2 Two differential LVPECL or LVDS output pairs selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, Two selectable differential PCLKx, nPCLKx input pairs nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The PCLKx, nPCLKx pairs can accept the following differential fully differential architecture and low propagation delay make it ideal input levels: LVPECL, LVDS, CML for use in clock distribution circuits. Maximum output frequency: 3GHz Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input Part-to-part skew: 100ps (maximum) Propagation delay: 565ps (typical) at 3.3V Additive phase jitter, RMS: 0.21ps (typical) at 3.3V Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pullup OE VCC CLK SEL 1 16 PCLK0 2 15 VEE Pulldown CLK SEL nPCLK0 3 14 Q0 13 nQ0 PCLK1 4 nPCLK1 12 Q1 5 Pulldown PCLK0 nc 6 11 nQ1 Pullup/Pulldown 0 nPCLK0 Q0 OE 7 10 VEE SEL OUT 8 9 nQ0 ICS859S0212I Q1 Pulldown PCLK1 nQ1 Pullup/Pulldown 1 16-Lead TSSOP nPCLK1 4.4mm x 5.0mm x 0.925mm package body G Package Top View Pullup SEL OUT ICS859S0212BGI REVISION A JUNE 4, 2012 1 2012 Integrated Device Technology, Inc.ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER Table 1. Pin Descriptions Number Name Type Description 1 CLK SEL Input Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels. 2 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 3 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 4 PCLK1 Input Pulldown Non-inverting differential clock input. Pullup/ 5 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 6 nc Unused No connect. 7 OE Input Pullup Output enable pin. See Table 4B. LVCMOS/LVTTL interface levels. Output select pin. When LOW, selects LVDS levels. When HIGH, selects LVPECL 8 SEL OUT Input Pullup levels. LVCMOS/LVTTL interface levels. See Table 3B. 9V Power Positive supply pin. See Table 3A. CC TAP 10, 15 V Power Negative supply pins. EE 11, 12 nQ1, Q1 Output Differential output pair. LVPECL or LVDS interface levels. 13, 14 nQ0, Q0 Output Differential output pair. LVPECL or LVDS interface levels. 16 V Power Positive supply pin. CC NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN R RPullup/Pulldown Resistor 75 k VCC/2 ICS859S0212BGI REVISION A JUNE 4, 2012 2 2012 Integrated Device Technology, Inc.