AP7176B 3A ULTRA LOW DROPOUT LINEAR REGULATOR WITH ENABLE Description Pin Assignments The AP7176B is a 3.0A ultra low-dropout (LDO) linear regulator that features an enable input and a power-good output. The enable input and power-good output allow users to configure power management solutions that can meet the sequencing requirements of FPGAs, DSPs, and other applications with different start-up and power-down requirements. The AP7176B features two supply inputs, for power conversion supply and control. With the separation of the control and the power input very low dropout voltages can be reached and power dissipation is reduced. A precision reference and feedback control deliver 1.5% accuracy over load, line, and operating temperature ranges. The AP7176B is available in SO-8EP, MSOP-8EP and U-DFN3030- 10 package with an exposed PAD to reduce the junction to case resistance and extend the temperature range it can be used in. (Top View) Features 1 10 VCNTL VOUT V Range: 1.2V to 3.65V V 3.0V to 5.5V IN CNTL 2 9 Adjustable Output Voltage VOUT VIN 8 Continuous Output Current I = 3A 3 OUT VOUT VIN GND Fast Transient Response 4 7 FB VIN Power on reset monitoring on V and V CNTL IN 5 6 11 PG EN Internal Soft-Start Stable with Low ESR MLCC Capacitors U-DFN3030-10 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Applications Notebook PC Netbook Wireless Communication Server Motherboard Dongle Front Side Bus VTT (1.2V/3.3A) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See AP7176B Typical Applications Circuit Figure 1 Typical Application Circuit Pin Descriptions Pin Pin Number Function Name SO-8EP MSOP-8EP U-DFN3030-10 Power Good.Output open drain to indicate the status of V via monitoring the FB pin. OUT PG 1 1 5 This pin is pulled low when the voltage is outside the limits, during thermal shutdown and if either V or V go below their thresholds. CNTL IN Enable Pin. Driving this pin low will disable the part. When left floating an internal current EN 2 2 6 source will pull this pin high and enable it. Power Input Pin for current supply. Connect a decoupling capacitor ( 10F) as close as VIN 3 3 7,8,9 possible to the pin for noise filtering BIAS supply for the controller, recommended 5V. Connect a decoupling capacitor ( 1F) VCNTL 4 4 10 as close as possible to the pin for noise filtering. NC 5 5 No Connection V 6 6 1,2,3 Power output pin OUT FB 7 7 4 Feedback to set the output voltage via an external resistor divider between V and GND OUT GND 8 8 11 Ground PAD EP EP EP Exposed pad connected to GND for good thermal conductivity Functional Block Diagram 2 of 14 April 2014 AP7176B Diodes Incorporated www.diodes.com Document number: DS35818 Rev.3 - 2 NEW PRODUCT