CY29946 2.5 V or 3.3 V, 200 MHz, 1:10 Clock Distribution Buffer 2.5 V or 3.3 V, 200 MHz, 1:10 Clock Distribution Buffer Features Functional Description 2.5 V or 3.3 V operation The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL 200 MHz clock support compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All Two LVCMOS-/LVTTL-compatible inputs other control inputs are LVCMOS/LVTTL compatible. The Ten clock outputs: drive up to 20 clock lines 10 outputs are LVCMOS or LVTTL compatible and can drive 50 series or parallel terminated transmission lines. For series 1 or 1/2 configurable outputs terminated transmission lines, each output can drive one or two Output three-state control traces giving the device an effective fanout of 1:20. The CY29946 is capable of generating 1 and 1/2 signals from 250-ps max output-to-output skew a 1 source. These signals are generated and retimed internally Pin-compatible with MPC946, MPC9446 to ensure minimal skew between the 1 and 1/2 signals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1 to1/2 Available in commercial and industrial temperature range outputs. 32-pin TQFP package The CY29946 outputs can also be three-stated via MR/OE input. When MR/OE is set HIGH, it resets the internal flip-flops and three-states the outputs. For a complete list of related documentation, click here. Block Diagram TCLK SEL 0 /1 TCLK0 3 QA0:2 /2 TCLK1 R 1 DSELA 0 /1 3 QB0:2 /2 R 1 DSELB /1 0 4 QC0:3 /2 1 R DSELC MR/OE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07286 Rev. *K Revised May 29, 2017CY29946 Pin Configuration TCLK SEL 1 24 VSS VDD 2 23 QB0 TCLK0 3 22 VDDC TCLK1 4 21 QB1 CY29946 DSELA 5 20 VSS DSELB 6 19 QB2 DSELC 7 18 VDDC VSS 8 17 VDDC Pin Description 1 Pin Name PWR I/O Description 3, 4 TCLK(0,1) I, PU External Reference/Test Clock Input 26, 28, 30 QA(2:0) VDDC O Clock Outputs 19, 21, 23 QB(2:0) VDDC O Clock Outputs 10, 12, 14, 16 QC(0:3) VDDC O Clock Outputs 5, 6, 7 DSEL(A:C) I, PD Divider Select Inputs. When HIGH, selects 2 input divider. When LOW, selects 1 input divider. 1 TCLK SEL I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. 32 MR/OE I, PD Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. If more than 1 Bank is being used in /2 Mode, a reset must be performed (MR/OE Asserted High) after power-up to ensure all internal flip-flops are set to the same state. 9, 13, 17, 18, 22, VDDC 2.5 V or 3.3 V Power Supply for Output Clock Buffers 25, 29 2 VDD 2.5 V or 3.3 V Power Supply 8, 11, 15, 20, 24, VSS Common Ground 27, 31 Note 1. PD = Internal pull-down. PU = Internal pull-up. Document Number: 38-07286 Rev. *K Page 2 of 9 VDDC 9 32 MR/OE QC0 10 31 VSS VSS 11 30 QA0 QC1 12 29 VDDC VDDC 13 28 QA1 QC2 14 27 VSS VSS 15 26 QA2 QC3 16 25 VDDC