Document Number: MPC5566 Freescale Rev. 3, September 2012 Data Sheet: Technical Data MPC5566 Microcontroller Data Sheet Contents This document provides electrical specifications, pin 1 Overview . 1 assignments, and package diagrams for the MPC5566 2 Ordering Information 3 microcontroller device. For functional characteristics, 3 Electrical Characteristics . 4 refer to the MPC5566 Microcontroller Reference 3.1 Maximum Ratings 4 Manual. 3.2 Thermal Characteristics 5 3.3 Package . 8 3.4 EMI (Electromagnetic Interference) Characteristics 8 3.5 ESD (Electromagnetic Static Discharge) Characteris- 1 Overview tics9 3.6 Voltage Regulator Controller (VRC) and The MPC5566 microcontroller (MCU) is a member of Power-On Reset (POR) Electrical Specifications9 the MPC5500 family of microcontrollers built on the 3.7 Power-Up/Down Sequencing 10 3.8 DC Electrical Specifications 14 Power Architecture embedded technology. This family 3.9 Oscillator and FMPLL Electrical Characteristics 20 of parts has many new features coupled with high 3.10 eQADC Electrical Characteristics . 22 performance CMOS technology to provide substantial 3.11 H7Fa Flash Memory Electrical Characteristics . 23 3.12 AC Specifications . 24 reduction of cost per feature and significant performance 3.13 AC Timing . 26 improvement over the MPC500 family. 3.14 Fast Ethernet AC Timing Specifications 46 4 Mechanicals 50 The host processor core of this device complies with the 4.1 MPC5566 416 PBGA Pinout . 50 Power Architecture embedded category that is 100% 4.2 MPC5566 416-Pin Package Dimensions . 53 5 Revision History for the MPC5566 Data Sheet . 55 user-mode compatible (including floating point library) 5.1 Information Changed Between Revisions 2.0 and 3.0 with the original PowerPC instruction set.The embedded 55 architecture enhancements improve the performance in 5.2 Information Changed Between Revisions 1.0 and 2.0 55 embedded applications. The core also has additional 5.3 Information Changed Between Revisions 0.0 and 1.0 instructions, including digital signal processing (DSP) 57 instructions, beyond the original PowerPC instruction set. Freescale Inc., 2008,2012. All rights reserved.Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565x. The host processor core of the MPC5566 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to significantly reduce the code size footprint. The MPC5566 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB) unified cache. The next level in the hierarchy contains the 128-KB on-chip internal SRAM and three- megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data. The external bus interface is designed to support most of the standard memories used with the MPC5xx family. The complex input/output timer functions of the MPC5566 are performed by two enhanced time processor unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language. The less complex timer functions of the MPC5566 are performed by the enhanced modular input/output system (eMIOS). The eMIOS 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIOs) signals. The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC).s 40-channels. The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps Ethernet/IEEE 802.3 networks and is compatible with three different standard MAC (media access controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or 100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and DMA support. MPC5566 Microcontroller Data Sheet, Rev. 3 2 Freescale Semiconductor