89HPES32H8G3 32-Lane 8-Port PCIe Gen3 Data Sheet System Interconnect Switch Per lane SerDes configuration Device Overview Full back channel equalization support The 89HPES32H8G3 is a 32-lane, 8-port system interconnect switch optimized for PCI Express Gen3 packet switching in high-performance Rx, 5 tap DFE applications, supporting multiple simultaneous peer-to-peer traffic flows. Rx, single tap has pulse shaping Target applications include servers, storage, communications, Rx CTLE compensates for up to 25db 4G/s embedded systems, and multi-host or intelligent I/O based systems with Tx De-emphasis inter-domain communication. Tx pre-shoot Programmable Drive strength Features Tx Margin High Performance Non-Blocking Switch Architecture Switch Partitioning 32-lane 8-port PCIe switch IDT proprietary feature that creates logically independent Seven x4 ports switch ports switches in the device Integrated SerDes supports 8.0 GT/s Gen3, 5.0 GT/s Gen2 Supports up to 8 fully independent switch partitions and 2.5 GT/s Gen1 operation Configurable downstream port device numbering Delivers up to 32 GBps (256 Gbps) of switching capacity Supports dynamic reconfiguration of switch partitions Supports 128 Bytes to 2 KB maximum payload size Dynamic port reconfiguration downstream, upstream Low latency cut-through architecture Dynamic migration of ports between partitions Supports one virtual channel and eight traffic classes Movable upstream port within and between switch partitions Standards and Compatibility Initialization / Configuration PCI Express Base Specification 3.0 compliant Supports Root (BIOS, OS, or driver), Serial EEPROM, or Implements the following optional PCI Express features SMBus switch initialization Advanced Error Reporting (AER) on all ports Common switch configurations are supported with pin strap- End-to-End CRC (ECRC) ping (no external components) Access Control Services (ACS) Supports in-system Serial EEPROM initialization/program- Power Budgeting Enhanced Capability ming Device Serial Number Enhanced Capability Quality of Service (QoS) Sub-System ID and Sub-System Vendor ID Capability Port arbitration Internal Error Reporting ECN Round robin Atomic operations ECN Request metering TLP processing hints ECN IDT proprietary feature that balances bandwidth among Latency Tolerance Reporting (LTR) ECN switch ports for maximum system throughput Optimized Buffer Flush/Fill (OBFF) ECN High performance switch core architecture ARI ECN Combined Input Output Queued (CIOQ) switch architecture VGA and ISA enable with large buffers L0s and L1 ASPM Clocking Port Configurability Supports 100 MHz reference clock frequency x4 and x8 ports Flexible port clocking modes Ability to merge adjacent x4 ports to create a x8 port Common clock Automatic per port link width negotiation Non-common clock (x8 x4 x2 x1) Local port clock with SSC and port reference clock input Crosslink support Hot-Plug and Hot Swap Automatic lane reversal Hot-plug controller on all ports Autonomous and software managed link width and speed Hot-plug supported on all downstream switch ports control IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 38 April 17, 2013 2013 Integrated Device Technology, IncIDT 89HPES32H8G3 Data Sheet All ports support hot-plug using low-cost external SMBus I/O Product Description expanders Utilizing standard PCI Express Gen3 interconnect, the PES32H8G3 Configurable presence detect supports card and cable appli- provides the most efficient system interconnect switching solution for cations applications requiring high throughput, low latency, and simple board GPE output pin for hot-plug event notification layout with a minimum number of board layers. It provides 32 GBps Enables SCI/SMI generation for legacy operating system (256 Gbps) of aggregated, full-duplex switching capacity through 32 support integrated serial lanes, using proven and robust IDT technology. Each Hot swap capable I/O lane is capable of 8 GT/s of bandwidth in both directions and is fully compliant with PCI Express Base specification 3.0. Power Management Supports D0, D3hot and D3 power management states The PES32H8G3 is based on a flexible and efficient layered archi- tecture. The PCI Express layer consists of SerDes, Physical, Data Link Active State Power Management (ASPM) and Transaction layers in compliance with PCI Express Base specifica- Supports L0, L0s, L1, L2/L3 Ready and L3 link states tion Revision 3.0. The PES32H8G3 can operate either as a store and Configurable L0s and L1 entry timers allow performance/ forward or cut-through switch. It supports eight Traffic Classes (TCs) power-savings tuning and one Virtual Channel (VC) with sophisticated resource management Supports PCI Express Power Budgeting Capability to enable efficient switching and I/O connectivity for servers, storage, SerDes power savings and embedded processors with limited connectivity. Supports low swing / half-swing SerDes operation The PES32H8G3 is a partitionable PCIe switch. This means that in SerDes optionally turned-off in D3hot addition to operating as a standard PCI express switch, the SerDes associated with unused ports are turned-off PES32H8G3 ports may be partitioned into groups that logically operate SerDes associated with unused lanes are placed in a low as completely independent PCIe switches. Figure 2 illustrates a three power state partition PES32H8G3 configuration. 9 General Purpose I/O Reliability, Availability and Serviceability (RAS) ECRC support AER on all ports SECDED ECC protection on all internal RAMs End-to-end data path parity protection Checksum Serial EEPROM content protected Autonomous link reliability (preserves system operation in the presence of faulty links) Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug On-die scope On-chip link activity and status outputs available for several ports including the upstream ports Per port link activity and status outputs available using external SMBus I/O expander for all remaining ports SerDes test modes Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Power Supplies Requires three power supply voltages (1.0V, 1.8V, and 3.3V) No power sequencing requirements Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with 1mm ball spacing 2 of 38 April 17, 2013