SLAVE SERIAL MODULATION CONTROL MASTER CONTROL DATASHEET ISL5314 FN4901 Rev 3.00 Direct Digital Synthesizer January 19, 2010 The 14-bit ISL5314 provides a complete Direct Digital Features Synthesizer (DDS) system in a single 48 Ld LQFP package. 125MSPS output sample rate with 5V digital supply A 48-bit Programmable Carrier NCO (numerically controlled oscillator) and a high speed 14-bit DAC (digital-to-analog 100MSPS output sample rate with 3.3V digital supply converter) are integrated into a stand alone DDS. 14-bit digital-to-analog (DAC) with internal reference The DDS accepts 48-bit center and offset frequency control Parallel control interface for fast tuning (50MSPS control information via a parallel processor interface. A 40-bit register write rate) and serial control interface frequency tuning word can also be loaded via an asynchronous 48-bit programmable frequency control serial interface. Modulation control is provided by 3 external pins. The PH0 and PH1 pins select phase offsets of 0, 90, Offset frequency register and enable pin for fast FSK 180 and 270, while the ENOFR pin enables or zeros the Small 48 Ld LQFP packaging offset frequency word to the phase accumulator. Pb-Free (RoHS compliant) The parallel processor interface has an 8-bit write-only data input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe Applications (WR), and a Write Enable (WE). The processor can update Programmable local oscillator all registers simultaneously by loading a set of master registers, then transfer all master registers to the slave FSK, PSK modulation registers by asserting the UPDATE pin. Direct digital synthesis Ordering Information Clock generation PART PART TEMP. PACKAGE PKG. NUMBER MARKING RANGE (C) (Pb-free) DWG. Pinout ISL5314 ISL5314INZ ISL5314 INZ -40 to +85 48 Ld LQFP Q48.7x7A (48 LD LQFP) ISL5314EVAL2 25 Evaluation Board TOP VIEW NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 48 47 46 45 44 43 42 41 40 39 3837 A2 36 2. For Moisture Sensitivity Level (MSL), please see device information page for C2 1 ISL5314. For more information on MSL please see techbrief TB363. 35 A3 C1 2 34 PH0 C0 3 33 ENOFR PH1 4 Block Diagram 32 SSYNC DGND 5 DVDD 31 CLK 6 ISL5314 30 SCLK DVDD 7 C(7:0) 29 DGND RESET 8 A(3:0) PHASE DGND 28 UPDATE 9 ACCUM. WR 27 SDATA COMPOUT 10 IN- WE - + 26 DVDD REFLO IN+ 11 25 DGND REFIO 12 UPDATE 13 14 15 16 17 18 19 20 21 22 23 24 SDATA COMP1 COMP2 SSYNC SINE SCLK 14 BIT WAVE IOUTA DAC ROM IOUTB ENOFR INT REFIO PH(1:0) REF REFLO RESET CLK FN4901 Rev 3.00 Page 1 of 17 January 19, 2010 COMPOUT FSADJ C3 COMP1 C4 AGND C5 AGND C6 IOUTB C7 IOUTA DVDD COMP2 WR AVDD DGND AGND WE IN+ NC IN- A0 AGND A1 ISL5314 Pin Descriptions PIN NO. PIN NAME TYPE PIN DESCRIPTION 44-48, 1-3 C(7:0) Input 8-bit processor input data bus. C7 is the MSB. Data is written to the control register selected on A(3:0) on the rising edge of WR when WE is active. 42 WR Input Write clock for the processor interface. Parallel data is clocked into the chip on the rising edge of WR. 40 WE Input Write enable. Active low. WE must be active when writing data to the chip. 35-38 A(3:0) Input Processor interface address bus. These pins select the destination register for data on the C(7:0) bus. A3 is the MSB. 6 CLK Clock NCO and DAC clock. The phase accumulator and DAC output update on the rising edge of this clock. CLK can be asynchronous to the WR clock. 8 RESET Input Reset. Active low. Resets control registers to their default states (see register description table) and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur. 30 SCLK Input Serial clock. Polarity is programmable. See control word 12. May be asynchronous to CLK. If not used, connect to DGND. 27 SDATA Input Serial data. See control word 12. If not used, connect to DGND. 32 SSYNC Input Serial sync. See control word 12. If not used, connect to DGND. 9UPDATE Input Active low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0) pins. This pin is provided for updating an entire frequency word at once rather than byte by byte. 33, 34 PH(1:0) Input Phase offset bits. The phase of the output is shifted. If not used, these pins should be grounded. 00 0 reference 01 90 shift 10 180 shift 11 270 shift 4 ENOFR Input Enable offset frequency. Active high. When high, the offset frequency bus is enabled to the phase accumulator. When low, the offset frequency bus is zeroed. This pin does not affect the contents of the offset frequency registers. If not used, the pin should be grounded. 10 COMPOUT Output Comparator output. 11 REFLO Input Connect to analog ground to enable the DACs internal 1.2V reference or connect to AV to DD disable the internal reference. 12 REFIO Input Reference voltage input for the DAC if internal reference is disabled. Recommend the use of a 0.1F cap to ground from the REFIO pin when a DC reference voltage is used. 13 FSADJ Full scale current adjust for the DAC. Use a resistor to ground (R ) to adjust the full scale SET output current. Full Scale Output Current = 32 x V /R , where V equals the FSADJ SET FSADJ reference voltage. 14 COMP1 Noise reduction for the DAC. Connect a 0.1F cap to AV plane. DD 19 COMP2 Noise reduction for the DAC. Connect a 0.1F cap to AGND plane. 18 IOUTA Output DAC current output. 17 IOUTB Output DAC complementary current output. 20 AVDD Power Analog supply voltage. 15, 16, 21, 24 AGND GND Analog ground. 7, 26, 31, 43 DVDD Power Digital supply voltage. 5, 25, 28, 29, 41 DGND GND Digital ground. 22, 23 IN+, IN- Input Comparator inputs. To power down the comparator, connect both of these pins to the analog power supply. This will conserve ~4mA of current. 39 NC NC No connect. FN4901 Rev 3.00 Page 2 of 17 January 19, 2010