M24128-DFCS6TP/K

M24128-BW M24128-BR M24128-BF M24128-DF 128-Kbit serial IC bus EEPROM Datasheet - production data Features 2 Compatible with all I C bus modes: 1 MHz 400 kHz 100 kHz Memory array: TSSOP8 (DW) 128 Kbit (16 Kbyte) of EEPROM 169 mil width Page size: 64 byte Additional Write lockable page (M24128-D order codes) Single supply voltage and high speed: 1 MHz clock from 1.7 V to 5.5 V SO8 (MN) Write: 150 mil width Byte Write within 5 ms Page Write within 5 ms Operating temperature range: from -40 C up to +85 C Random and sequential Read modes Write protect of the whole memory array UFDFPN8 (MC) Enhanced ESD/Latch-Up protection DFN8 - 2x3 mm More than 4 million Write cycles More than 200-years data retention Packages SO8 ECOPACK2 UFDFPN5 (MH) WLCSP (CS) TSSOP8 ECOPACK2 DFN5 - 1.7x1.4 mm UFDFPN8 ECOPACK2 WLCSP ECOPACK2 UFDFPN5 ECOPACK2 Unsawn wafer (each die is tested) Unsawn wafer September 2017 DocID16892 Rev 30 1/46 This is information on a product in full production. www.st.comContents M24128-BW M24128-BR M24128-BF M24128-DF Contents 1 Description . 6 2 Signal description . 8 2.1 Serial Clock (SCL) . 8 2.2 Serial Data (SDA) 8 2.3 Chip Enable (E2, E1, E0) 8 2.4 Write Control (WC) . 8 2.5 V (ground) . 8 SS 2.6 Supply voltage (V ) . 9 CC 2.6.1 Operating supply voltage (V ) 9 CC 2.6.2 Power-up conditions 9 2.6.3 Device reset . 9 2.6.4 Power-down conditions 9 3 Memory organization . 10 4 Device operation . 11 4.1 Start condition 12 4.2 Stop condition 12 4.3 Data input . 12 4.4 Acknowledge bit (ACK) 12 4.5 Device addressing 13 5 Instructions . 14 5.1 Write operations 14 5.1.1 Byte Write . 15 5.1.2 Page Write . 16 5.1.3 Write Identification Page (M24128-D only) 17 5.1.4 Lock Identification Page (M24128-D only) . 17 5.1.5 ECC (Error Correction Code) and Write cycling 17 5.1.6 Minimizing Write delays by polling on ACK 18 5.2 Read operations 19 5.2.1 Random Address Read . 20 2/46 DocID16892 Rev 30