W5100S (W5100S-L & W5100S-Q) Version 1.0.0 W5100S W5100S designed with Hardwired TCP/IP, WIZnet technology, is an embedded Internet Controller Chip. W5100S supporting Full Hardwired, Ethernet MAC (Media Access Control), and 10Base-T/100Base-TX Ethernet PHY is Internet Connectivity One-chip Solution for Internet Protocol (TCP/IP). With W5100S, Host (User MCU) simply handles variety Internet Protocol such as IPv4, TCP, UDP, ICMP, IGMP, ARP, PPPoE and etc. And W5100S supports each 8KB Memory for Transmit and Receive to minimize using memory on Low-end level Host. Host also independently uses 4 Hardwired SOCKETs to develop vary Internet Applications in each Hardwired SOCKETs. W5100S supports SPI and Parallel System BUS Interface for Host Interface. It also provides Low Power / Low Heat design, WOL (Wake On LAN), Ethernet PHY Power Down Mode and etc. W5100S is Low-cost chip that improves on W5100. Any Firmware using on W5100 can be used on W5100S without any modification. Also, W5100S has 48 Pin LQFP & QFN Lead-Free Package, smaller than W5100 for product miniaturization. 2 / 109 W5100S Datasheet Version1.0.0