SKU86 Zipcores

BT 656 ENCODER BT.656 Encoder with Colour-Space Converter Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Converts 24-bit RGB digital video to an industry standard 8-bit ITU-R BT.656 stream Integrated RGB888 to 4:2:2 YCbCr colour-space converter Both PAL and NTSC (576i and 480i) formats supported All signals synchronous with the pixel clock Small implementation size ideal for all types of FPGA Compatible with a wide range of SD video encoder ICs Applications Figure 1: BT.656 Encoder architecture BT.656 output video generation General Description PAL & NTSC SDTV video format conversion Connectivity with a wide range of commercially available video BT 656 ENCODER (Figure 1) is a digital video encoder with integrated encoder ICs colour-space converter. The encoder accepts 24-bit RGB pixels from sequential odd and even fields. These pixels are then mapped to the Simple and cost-effective method for generating digital video YCbCr colour-space and formatted correctly into a BT.656 output stream. outputs from your FPGA or ASIC The encoder begins operation after reset is de-asserted and on detection of input field 0 . Input pixels are sampled on the rising-edge of clk when Generic Parameters the pixin val and pixin rdy signals are both asserted high. The pixin vsync and the pixin hsync flags are coincident with the first pixel of a field and line. The pixin field flag indicates whether the field is odd or even. Generic name Description Type Valid range mode Output video mode integer 0: PAL (576i) The valid-ready flow-control interface shares a common format with all 1: NTSC (480i) other Zipcores video IP and allows easy connectivity between IP cores. The valid-ready interface also allows simple connectivity with an input FIFO or external frame buffer. Pin-out Description The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video val signal that is asserted with the first valid byte of the output stream. Pin name I/O Description Active state If the encoder is starved of pixels during the generation of an active line clk in Pixel clock rising edge then the underflow flag will be asserted. In the event of an underflow reset in Asynchronous reset low condition, then design must be reset by asserting the reset signal low for at least one clock cycle. Operation will then resume as normal when the underflow out Pixel underflow error high next input field is detected. video out 7:0 out BT.656 output video (8-bit) data video val out BT.656 output video valid high BT.656 Encoder pixin 23:0 in 24-bit RGB888 pixel data pixin field in Field flag 0: odd field The encoder samples the incoming RGB pixels and looks for the first 1: even field active line in field 0 (odd field). Once this is detected the generation of the BT.656 stream begins. Only active input pixels are processed by the pixin vsync in Vertical sync in high encoder. pixin hsync in Horizontal sync in high After all the lines in the odd field have been encoded, operation continues pixin val in Input pixel valid high with the encoding of all active lines in field 1 (even field). The encoder then reverts back to field 0 once again. pixin rdy out Ready to accept input pixel high (handshake signal) After a system reset, the encoder will revert to it s initial state and stop generating the output stream. Encoding will then resume again with the first active line of field 0 . Copyright 2014 www.zipcores.com Download this VHDL Core Page 1 of 3BT 656 ENCODER BT.656 Encoder with Colour-Space Converter Rev. 1.1 When the generic parameter mode is set to 0 , the encoder expects an Figure 3 shows the output BT.656 video stream from the encoder. Bytes 576i interlaced video input with a resolution of 720 x 288 pixels per field. are transferred on a rising clock-edge when video val is active high. Conversely, when mode is set to 1 then the expected input is (480i) or 720 x 240 pixels per field. Note that only active pixels should be sent to the encoder. The encoder input is not concerned with input pixels during periods of vertical or horizontal blanking. All video timing information is automatically embedded in the BT.656 output stream. Colour-space converter Figure 3: BT.656 output video stream The encoder features an integrated colour-space converter that converts the RGB inputs to YCbCr 4:2:2 format. Chroma values are decimated every second pixel to generate the 4:2:2 video. The colour-space Source File Description conversion is done according to the following formula: All source files are provided as text files coded in VHDL. The following table gives a brief explanation of each file. Y=16+0.257R+0.504G+0.098B Cb=1280.148R0.291G+0.439B Cr=128+0.439R0.368G0.071B Source file Description video in.txt Source input video text file Functional Timing pipeline reg.vhd Pipeline register element fifo sync.vhd Synchronous FIFO Example input waveforms are shown in Figure 2. Input pixels and syncs video file reader.vhd Input video text file reader are sampled on a rising clock-edge when pixin val and pixin rdy are both high. When pixin val is low then the inputs are ignored by the bt 656 enc sof.vhd Field sync component encoder. bt 656 enc csc.vhd Colour-space converter bt 656 enc 422.vhd Chroma re-sampler bt 656 enc pack.vhd Pixel packer component bt 656 enc unpack.vhd Pixel unpacker component bt 656 enc enc.vhd Main BT.656 formatter bt 656 encoder.vhd Top-level component bt 656 encoder bench.vhd Top-level testbench Functional Testing An example VHDL testbench is provided for use in a suitable VHDL simulator. The compilation order of the source code is as follows: 1. pipeline reg.vhd 2. fifo sync.vhd 3. bt 656 enc sof.vhd 4. bt 656 enc csc.vhd 5. bt 656 enc 422.vhd 6. bt 656 enc pack.vhd 7. bt 656 enc unpack.vhd 8. bt 656 enc.vhd 9. bt 656 encoder.vhd 10. bt 656 encoder bench.vhd 11. video file reader.vhd Figure 2: Input waveforms showing the start of a new field and start of a new line (pixin val shown with 50% duty-cycle) The VHDL testbench instantiates the BT 656 ENCODER component with the video format set to PAL or 576i. The source video for the simulation is generated by the file-reader component. This component reads a text-based file which contains the RGB pixels and flags on consecutive lines. The text file is called video in.txt and should be placed in the top-level simulation directory. Copyright 2014 www.zipcores.com Download this VHDL Core Page 2 of 3