VT2 854S057 4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination DATA SHEET General Description Features The 854S057 is a 4:1 or 2:1 LVDS Clock Multiplexer which can High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer operate up to 2GHz. The PCLK, nPCLK pairs can accept most standard differential input levels. Internal termination is provided on One LVDS output pair each differential input pair. The 854S057 operates using a 2.5V Four selectable PCLK, nPCLK inputs with internal termination supply voltage. The fully differential architecture and low propagation PCLKx, nPCLKx pairs can accept the following differential delay make it ideal for use in high speed multiplexing applications. input levels: LVPECL, LVDS, CML, SSTL The select pins have internal pulldown resistors. Leaving one input Maximum output frequency: 2GHz unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most Part-to-part skew: 200ps (maximum) significant bit and the binary number applied to the select pins will Propagation delay: 650ps (maximum) select the same numbered data input (i.e., 00 selects PCLK0, Additive phase jitter, RMS: 0.047ps (typical) nPCLK0). Full 2.5V power supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment VT0 VDD 1 20 VDD PCLK0 2 19 PCLK3 50 50 VT0 3 18 VT3 nPCLK0 4 17 nPCLK3 PCLK0 nPCLK0 SEL1 5 16 Q SEL0 6 15 nQ VT1 PCLK1 7 14 PCLK2 VT1 8 13 50 50 nPCLK1 9 12 nPCLK2 PCLK1 GND 10 11 GND nPCLK1 0 0 854S057 VT2 0 1 Q nQ 20-Lead TSSOP 1 0 50 50 4.4mm x 6.5mm x 0.925mm package body PCLK2 1 1 G Package nPCLK2 Top View VT3 50 50 PCLK3 nPCLK3 Pulldown SEL1 Pulldown SEL0 854S057 Rev A 10/23/14 1 2014 Integrated Device Technology, Inc.854S057 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 20 V Power Power supply pins. DD 2 PCLK0 Input Non-inverting LVPECL differential clock input. R = 50 termination to VT0. T 3 VT0 Input Termination input. For LVDS input, leave floating. R = 50 termination to VT0. T 4 nPCLK0 Input Inverting LVPECL differential clock input. R = 50 termination to VT0. T 5, 6 SEL1, SEL0 Input Pulldown Clock select inputs. LVCMOS/LVTTL interface levels. 7 PCLK1 Input Non-inverting LVPECL differential clock input. R = 50 termination to VT1. T 8 VT1 Input Termination input. For LVDS input, leave floating. R = 50 termination to VT1. T 9 nPCLK1 Input Inverting LVPECL differential clock input. R = 50 termination to VT1. T 10, 11 GND Power Power supply ground. 12 nPCLK2 Input Inverting LVPECL differential clock input. R = 50 termination to VT2. T 13 VT2 Input Termination input. For LVDS input, leave floating. R = 50 termination to VT2. T 14 PCLK2 Input Non-inverting LVPECL differential clock input. R = 50 termination to VT2. T 15, 16 nQ, Q Output Differential output pair. LVDS interface levels. 17 nPCLK3 Input Inverting LVPECL differential clock input. R = 50 termination to VT3. T 18 VT3 Input Termination input. For LVDS input, leave floating. R = 50 termination to VT3. T 19 PCLK3 Input Non-inverting LVPECL differential clock input. R = 50 termination to VT3. T NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pulldown Resistor 50 k PULLDOWN R Input Termination Resistor 40 50 60 T Table 3. Control Input Function Table Inputs Outputs SEL1 SEL0 PCLKx, nPCLKx 0 (default) 0 (default) PCLK0, nPCLK0 0 1 PCLK1, nPCLK1 1 0 PCLK2, nPCLK2 1 1 PCLK3, nPCLK3 Rev A 10/23/14 2 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION